ICS873990 Datasheet, PDF (7/16 Pages) Integrated Circuit Systems – LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS873990
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, V_CC = V_CCA = V_CCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
t_R / t_R
Input Rise/Fall Time TEST_CLK
Feedback ÷ 6
66.66
Reference Frequency
VCO_SEL = 0
Feedback ÷ 8
Feedback ÷ 16
Feedback ÷ 24
50
25
16.66
Feedback ÷ 32
12.5
f_REF
Feedback ÷ 4
50
Feedback ÷ 6
33.33
Reference Frequency
VCO_SEL = 1
Feedback ÷ 8
25
Feedback ÷ 16
12.5
Feedback ÷ 24
8.33
Feedback ÷ 32
6.25
f_REFDC
Reference Input Duty Cycle
25
NOTE: These parameters are guaranteed by design, but not tested in production.
Maximum
3
133.33
100
50
33.33
25
100
66.66
50
25
16.66
12.5
75
Units
ns
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
TABLE 7. AC CHARACTERISTICS, V_CC = V_CCA = V_CCO = 3.3V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
t(Ø)
tsk(o)
Output Frequency
Static Phase Offset;
NOTE 1, 5
TEST_CLK
Output Skew; NOTE 2, 3
400
-240
120
0
250
tsk(w) Multiple Frequency Skew; NOTE 3, 6
350
tjit(cc) Cycle-to-Cycle Jitter; NOTE 3
±50
VCO_SEL = 0
400
800
f_VCO
PLL VCO Lock Range; NOTE 4
VCO_SEL = 1
200
400
t_LOCK
t_R / t_F
odc
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
10
20% to 80%
0.2
1
45
55
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 2:Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: When VCO_SEL = 0, the PLL will be unstable with feedback configurations of ÷2, ÷4 and some ÷6.
When VCO_SEL = 1, the PLL will be unstable with a feedback configuration of ÷2.
NOTE 5: Static phase offset is specified for an input frequency of 50MHz with feedback in ÷8.
NOTE 6: Defined as skew across banks of outputs switching in the same direction operating at different frequencies
with the same supply voltages and equal load conditions. Measured at V_CCO/2.
Units
MHz
ps
ps
ps
ps
MHz
MHz
ms
ns
%
873990AY
www.icst.com/products/hiperclocks.html
7
REV. B JUNE 13, 2005