ICS873990 Datasheet, PDF (3/16 Pages) Integrated Circuit Systems – LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS873990
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
V
EE
2
MR
3
PLL_EN
4
REF_SEL
5
6
7
8
9, 10
11
12
FSEL_FB2
FSEL_FB1
FSEL_FB0
TEST_CLK
XTAL_IN,
XTAL_OUT
V_CC
EXT_FB
13
nEXT_FB
14
15,
16
17, 22, 30, 42
18, 19
V
CCA
nQFB,
QFB
V_CCO
nQD0, QD0
Power
Input
Input
Input
Input
Input
Input
Power
Input
Input
Power
Output
Power
Output
Negative supply pin.
Active High Master Reset. When logic HIGH, the internal dividers are
Pulldown
reset causing the true outputs (Qx) to go low and the inverted outputs
(nQx) to go high. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS/LVTTL interface levels.
Pulldown
PLL enable pin. When logic LOW, PLL is enabled. When logic HIGH,
PLL is in bypass mode. LVCMOS/LVTTL interface levels.
Selects between the different reference inputs as the PLL reference
Pulldown source. When logic LOW, selects crystal inputs. When logic HIGH,
selects TEST_CLK. LVCMOS/LVTTL interface levels.
Pulldown Feedback frequency select pins. LVCMOS/LVTTL interface levels.
Pulldown LVCMOS/LVTTL test clock input.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
Core supply pin.
Pulldown External feedback input.
Pullup/
Pulldown
External feedback input. V_CC/2 default when left floating.
Analog supply pin.
Differential feedback output pair. LVPECL interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
20, 21
nQD1, QD1 Output
Differential output pair. LVPECL interface levels.
23, 24
nQC0, QC0 Output
Differential output pair. LVPECL interface levels.
25, 26
27
33
36
39
28, 29
nQC1, QC1
FSEL3
FSEL2
FSEL1
FSEL0
nQC2, QC2
Output
Input
Output
Differential output pair. LVPECL interface levels.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
31, 32
nQB0, QB0 Output
Differential output pair. LVPECL interface levels.
34, 35
nQB1, QB1 Output
Differential output pair. LVPECL interface levels.
37, 38
nQB2, QB2 Output
Differential output pair. LVPECL interface levels.
40, 41
nQB3, QB3 Output
Differential output pair. LVPECL interface levels.
43, 44
nQA0, QA0 Output
Differential output pair. LVPECL interface levels.
45, 46
nQA1, QA1 Output
Differential output pair. LVPECL interface levels.
47, 48
nQA2, QA2 Output
Differential output pair. LVPECL interface levels.
49, 50
51
52
nQA3, QA3
SYNC_SEL
VCO_SEL
Output
Input
Input
Pulldown
Pulldown
Differential output pair. LVPECL interface levels.
Sync output select pin. When LOW, the SYNC output follows the
timing diagram (page 5). When HIGH, QD output follows QC output.
Selects VCO range. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
873990AY
www.icst.com/products/hiperclocks.html
3
REV. B JUNE 13, 2005