ICS844051I Datasheet, PDF (7/11 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844051I
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844051I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.V and V should
DD
DDA
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each V_DDA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
V_DD
V_DDA
3.3V or 2.5V
.01μF 10Ω
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844051I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for dif-
ferent board layouts.
X1
Crystal
XTAL_IN
C1
XTAL_OUT
C2
Figure 2. CRYSTAL INPUt INTERFACE
844051CGI
www.icst.com/products/hiperclocks.html
7
REV. A NOVEMBER 23, 2005