ICS844051I Datasheet, PDF (4/11 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844051I
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
TABLE 3D. LVDS DC CHARACTERISTICS, V_DD = V_DDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
V_OD
Δ V_OD
V_OS
Δ V_OS
Differential Output Voltage
V_OD Magnitude Change
Offset Voltage
V_OS Magnitude Change
Typical
350
400
1.4
50
Maximum
Units
mV
mV
V
mV
TABLE 3E. LVDS DC CHARACTERISTICS, V_DD = V_DDA = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
V_OD
Δ V_OD
V_OS
Δ V_OS
Differential Output Voltage
V_OD Magnitude Change
Offset Voltage
V_OS Magnitude Change
Typical
350
400
1.15
40
Maximum
Units
mV
mV
V
mV
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
Test Conditions
Minimum Typical Maximum
Fundamental
18.125
23.4375
50
7
1
Units
MHz
Ω
pF
mW
TABLE 5A. AC CHARACTERISTICS, V_DD = V_DDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
f_OUT
tjit(Ø)
t_R / t_F
odc
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
Output Duty Cycle
156.25MHz @ Integration Range:
1.875MHz - 20MHz
20% to 80%
NOTE 1: Please refer to the Phase Noise Plots following this section.
Minimum Typical Maximum Units
156.25
MHz
0.45
ps
300
ps
50
%
TABLE
5B.
AC
CHARACTERISTICS,
V
DD
=
V
DDA
=
2.5V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
f_OUT
tjit(Ø)
t_R / t_F
odc
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
Output Duty Cycle
156.25MHz @ Integration Range:
1.875MHz - 20MHz
20% to 80%
NOTE 1: Please refer to the Phase Noise Plots following this section.
Minimum Typical Maximum Units
156.25
MHz
0.45
ps
300
ps
50
%
844051CGI
www.icst.com/products/hiperclocks.html
4
REV. A NOVEMBER 23, 2005