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| ICS843101-312 Datasheet, PDF (7/14 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER | |||
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ADVANCE INFORMATION
Integrated
ICS843101-312
Circuit
Systems, Inc.
FEMTOCLOCKS⢠CRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 8A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
fOUT
tjit(Ã)
Output Frequency
RMS Phase Jitter; NOTE 1
Mode = LOW
312.5MHz, (1.875MHz - 20MHz)
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
S_DATA to
tS
Setup Time
S_CLOCK
S_CLOCK
to S_LOAD
10
10
tH
Hold Time
S_DATA to
S_CLOCK
10
NOTE 1: Characterized using a 25MHz crystal.
Typical
312.5
TBD
TBD
50
Maximum Units
MHz
ps
ps
%
ns
ns
ns
TABLE 8B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%,VCCO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
fOUT
tjit(Ã)
Output Frequency
RMS Phase Jitter; NOTE 1
Mode = LOW
312.5MHz, (1.875MHz - 20MHz)
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
S_DATA to
S_CLOCK
10
tS
Setup Time S_CLOCK
to S_LOAD
10
tH
Hold Time
S_DATA to
S_CLOCK
10
NOTE 1: Characterized using a 25MHz crystal.
Typical
312.5
TBD
TBD
50
Maximum Units
MHz
ps
ps
%
ns
ns
ns
TABLE 8C. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%,VCCO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
fOUT
tjit(Ã)
Output Frequency
RMS Phase Jitter; NOTE 1
Mode = LOW
312.5MHz, (1.875MHz - 20MHz)
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
S_DATA to
S_CLOCK
10
tS
Setup Time S_CLOCK
to S_LOAD
10
tH
Hold Time
S_DATA to
S_CLOCK
10
NOTE 1: Characterized using a 25MHz crystal.
Typical
312.5
TBD
TBD
50
Maximum Units
MHz
ps
ps
%
ns
ns
ns
843101AG-312
www.icst.com/products/hiperclocks.html
7
OCTOBER 18, 2005
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