ICS843101-312 Datasheet, PDF (2/14 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER

ADVANCE INFORMATION
Integrated
ICS843101-312
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
FUNCTIONAL DESCRIPTION
The ICS843101-312 features a fully integrated PLL and
therefore requires no external components for setting the
loop bandwidth. A 25MHz fundamental crystal is used as
the input to the on chip oscillator. The output of the osc-
illator is fed into the pre-divider. In frequency margining
mode, the 25MHz crystal frequency is divided by 2 and
a 12.5MHz reference frequency is applied to the phase
detector. The VCO of the PLL operates over a range of
560MHz to 690MHz. The output of the M divider is also
applied to the phase detector.
The default mode for the ICS843101-312 is 312.5MHz
output frequency using a 25MHz crystal. The output fre-
quency can be changed by placing the device into the
margining mode using the mode pin and using the serial
interface to program the M feedback divider. Frequency
margining mode operation occurs when the MODE input
is HIGH. The phase detector and the M divider force the
VCO output frequency to be M times the reference fre-
TABLE 1. FREQUENCY MARGIN FUNCTION TABLE
quency by adjusting the VCO control voltage. Note that for
some values of M (either too high or too low), the PLL will
not achieve lock. The output of the VCO is scaled by an
output divider prior to being sent to the LVPECL output
buffer. The divider provides a 50% output duty cycle. The
relationship between the crystal input frequency, the M
divider, the VCO frequency and the output frequency
is provided in Table 1. When changing back from fre-
quency margining mode to nominal mode, the device will
return to the default nominal configuration that will provide
312.5 MHz output frequency.
Serial operation occurs when S_LOAD is HIGH. Serial
data can be loaded in either the default mode or the fre-
quency margining mode. The 6-bit shift register is loaded
by sampling the S_DATA bits with the rising edge of
S_CLOCK. After shifting in the 6-bit M divider value,
S_LOAD is transitioned from HIGH to LOW which latches
the contents of the shift-register into the M divider control
register. When S_LOAD is LOW, any transitions of
S_CLOCK or S_DATA are ignored.
XTAL
(MHz)
25
25
25
25
25
25
25
25
25
25
25
Pre-Divider
Reference
Feedback
(P)
Frequency (MHz) Divider (M)
2
12.5
45
2
12.5
46
2
12.5
47
2
12.5
48
2
12.5
49
2
12.5
50
2
12.5
51
2
12.5
52
2
12.5
53
2
12.5
54
2
12.5
55
M-Data
(Binary)
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
VCO
(MHz)
562.5
575
587.5
600
612.5
625
637.5
650
662.5
675
687.5
Output
Output
Divider (N) Frequency (MHz)
2
281.25
2
287.5
2
293.75
2
300
2
306.25
2
312.5
2
318.75
2
325
2
331.25
2
337.5
2
343.75
%
Change
-10.0
-8.0
-6.0
-4.0
-2.0
0
2.0
4.0
6.0
8.0
10.0
SERIAL LOADING
S_CLOCK
S_DATA
S_LOAD
843101AG-312
M5 M4 M3 M2 M1 M0
tt
SH
t
S
Time
FIGURE 1. SERIAL LOAD OPERATIONS
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2
OCTOBER 18, 2005