ICS8344-01 Datasheet, PDF (7/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8344-01
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE
5.
AC
CHARACTERISTICS,
V
DD
=
V
DDO
=
3.3V±5%;
V
DD
=
3.3V
±
5%,
V
DDO
=
2.5V
±
5%;
V_DD = V_DDO = 2.5V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
f_MAX
Maximum Output Frequency
t_PD
Propagation Delay, NOTE 1
0MHz ≤ f ≤ 200MHz
2.5
tsk(b)
Bank Skew;
NOTE 2, 6
Q0 - Q7
Q8 - Q15
Q16 - Q23
Measured on the rising edge of
V_DDO/2
250
MHz
5
ns
85
ps
180
ps
100
ps
tsk(o) Output Skew; NOTE 3, 6
tsk(pp) Part-to-Part Skew; NOTE 4, 6
t_R
Output Rise Time; NOTE 5
t_F
Output Fall Time; NOTE 5
odc
Output Duty Cycle
Measured on the rising edge of
V_DDO/2
Measured on the rising edge of
V /2
DDO
30% to 70%
200
200
ps
900
ps
800
ps
30% to 70%
200
800
ps
0MHz ≤ f ≤ 200MHz
tCYCLE/2
- 0.25
tCYCLE/2
tCYCLE/2
+ 0.25
%
f = 200MHz
2.25
2.5
2.75
ns
t_EN
Output Enable Time; NOTE 5
f = 10MHz
5
ns
t_DIS
Output Disable TIme; NOTE 5
f = 10MHz
4
ns
All parameters measured at 200MHz and VPPtyp unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output crossing point.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as between outputs at the same supply voltages ane with equal load conditions. Measured at the
output differential cross points.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
8344AY-01
www.icst.com/products/hiperclocks.html
7
REV. B AUGUST 6, 2001