9DBV0941 Datasheet, PDF (7/17 Pages) Integrated Circuit Systems – Integrated terminations; save 36 resistors compared to standard HCSL outputs

9DBV0941 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T_COM or T_IND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Supply Voltage
VDDx
Supply voltage for core and analog
1.7
1.8
1.9
V
Output Supply Voltage
VDDIO
Low Voltage Supply LP-HCSL Outputs
0.9975 1.05-1.8 1.9
V
Ambient Operating
Temperature
Input High Voltage
Input Mid Voltage
Input Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
T_COM
Commmercial range
0
25
70
°C
1
T_IND
Industrial range
-40
25
85
°C
1
V_IH
Single-ended inputs, except SMBus
0.75 V_DD
V_DD + 0.3 V
V_IM
Single-ended tri-level inputs ('_tri' suffix)
0.4 V_DD
0.6 V_DD
V
V_IL
Single-ended inputs, except SMBus
-0.3
0.25 V_DD V
I_IN
Single-ended inputs, V_IN = GND, V_IN = VDD
-5
Single-ended inputs
5
uA
I_INP
V_IN = 0 V; Inputs with internal pull-up resistors
-200
200
uA
V_IN = VDD; Inputs with internal pull-down resistors
F_in
1
200
MHz
2
L_pin
7
nH
1
C_IN
Logic Inputs, except DIF_IN
1.5
5
pF
1
C_{INDIF_IN}
DIF_IN differential clock inputs
1.5
2.7
pF
1,6
C_OUT
Output pin capacitance
6
pF
1
T_STAB
From V_DD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1
ms
1,2
Input SS Modulation
Frequency PCIe
f_MODINPCIe
Allowable Frequency for PCIe Applications
(Triangular Modulation)
30
33
kHz
Input SS Modulation
Frequency non-PCIe
f_MODIN
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
0
66
kHz
OE# Latency
t_LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1
3
clocks 1,3
Tdrive_PD#
t_DRVPD
DIF output enable after
PD# de-assertion
300
us
1,3
Tfall
t_F
Fall time of single-ended control inputs
Trise
t_R
Rise time of single-ended control inputs
SMBus Input Low Voltage V_ILSMB
V_DDSMB = 3.3V, see note 4 for V_DDSMB < 3.3V
SMBus Input High Voltage V_IHSMB
V_DDSMB = 3.3V, see note 5 for V_DDSMB < 3.3V
2.1
SMBus Output Low Voltage V_OLSMB
@ I_PULLUP
SMBus Sink Current
I_PULLUP
@ V_OL
4
Nominal Bus Voltage
V_DDSMB
Bus Voltage
1.7
SCLK/SDATA Rise Time
t_RSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA Fall Time
t_FSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
SMBus Operating
Frequency
f_MAXSMB
Maximum SMBus operating frequency
5
ns
2
5
ns
2
0.8
V
4
3.3
V
5
0.4
V
mA
3.6
V
1000
ns
1
300
ns
1
400
kHz
7
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{Control input must be monotonic from 20% to 80% of input swing.}
3_{Time from deassertion until outputs are >200 mV}
4 _{For VDDSMB < 3.3V, VILSMB <= 0.35VDDSMB}
5 _{For VDDSMB < 3.3V, VIHSMB >= 0.65VDDSMB}
6_{DIF_IN input}
7_{The differential input clock must be running for the SMBus to be active}
REVISION B 08/28/14
7
9 O/P 1.8V PCIE GEN1-2-3 FAN-OUT BUFFER W/ZO=100OHMS