9DBV0941 Datasheet, PDF (4/17 Pages) Integrated Circuit Systems – Integrated terminations; save 36 resistors compared to standard HCSL outputs

9DBV0941 DATASHEET
Pin Descriptions (cont.)
40 GND
41 DIF6
42 DIF6#
GND
OUT
OUT
43 vOE6#
IN
44 DIF7
45 DIF7#
OUT
OUT
46 vOE7#
IN
47 VDDIO
PWR
48 ^CKPWRGD_PD#
IN
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
9 O/P 1.8V PCIE GEN1-2-3 FAN-OUT BUFFER W/ZO=100OHMS
4
REVISION B 08/28/14