ICS97ULP845A Datasheet, PDF (6/12 Pages) Integrated Circuit Systems – 1.8V Low-Power Wide-Range Frequency Clock Driver

ICS97UL P 8 45A
Timing R equirements
Com mercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;
Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
M ax clock frequency
Application Frequency
Range
freq_op
1.8V+0.1V @ 25°C
95
freq_App
1.8V+0.1V @ 25°C
160
Input clock duty cycle
d_tin
30
CLK stabilization
T _{S TA B}
TYP
2.4
MAX UNITS
370 MHz
350 MHz
70
%
2.95
µs
Switching Characteristics¹
Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;
Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
Output enable time
Output disable time
Period jitter
Half-period jitter
Input slew rate
Output clock slew rate
Cycle-to-cycle period jitter
Dynamic Phase Offset
Static Phase Offset
Output to Output Skew
SSC modulation frequency
SSC clock input frequency
deviation
PLL Loop bandwidth (-3 dB
from unity gain)
t_en
t_dis
t_{jit (per)}
t_jit(hper)
SLr1(i)
SLr1(o)
t _{jit (c c +)}
t_jit(cc-)
t_{( )dyn}
t
2
SPO
t_skew
OE to any output
OE to any output
Input Clock
Output Enable (OE), (OS)
Notes:
1. Switching characteristics guaranteed for application frequency range.
2. Static phase offset shifted by design.
MIN
-30
-60
1
0.5
1.5
0
0
-20
-50
30.00
0.00
2.0
TYP
4.73
5.82
2.5
2.5
0
MAX
8
8
30
60
4
3
40
-40
20
50
50
33
UNITS
ns
ns
ps
ps
v/ns
v/ns
v/ns
ps
ps
ps
ps
ps
kHz
-0.50 %
MHz
1109D—06/19/07
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