ICS97ULP845A Datasheet, PDF (1/12 Pages) Integrated Circuit Systems – 1.8V Low-Power Wide-Range Frequency Clock Driver

Integrated
Circuit
Systems, Inc.
ICS97UL P 8 45A
1.8V Low-Power Wide-Range Frequency Clock Driver
Recommended Application:
• DDR2 Memory Modules / Zero Delay Buffer Fan Out
• Provides complete DDR DIMM logic solution
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 5 differential clock distribution (SSTL_18)
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• Auto PD when input signal is at a certain logic state
Switching Characteristics:
• Period jitter: 40ps
• Half-period jitter: 60ps
• CYCLE - CYCLE jitter 40ps
• OUTPUT - OUTPUT skew: 40ps
Pin Configuration
12 3 4 5
A
B
C
D
E
F
28-Ball BGA
Top View
Block Diagram
OE
OS
AV_DD
Powerdown
Control and
Test Logic
LD* or OE
LD*
PLL bypass
CLK_INT
CLK_INC
10K-100k
PLL
GND
FB_INT
FB_INC
* The Logic Detect (LD) powers down the device when a
logic low is applied to both CLK_INT and CLK_INC.
1109D—06/19/07
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
Ball Assignments
1
2
A
CLKT0
CLKC0
B CK_INT
V_DD
C CK_INC
OE
D
AGND
GND
E
AVDD
GND
3
CLKC1
NB
V_DD
V_DD
NB
4
CLKT1
5
FB_INT
V_DD
FB_INC
OS
FB_OUTC
GND FB_OUTT
GND
CLKT2
FB_OUTT
F
FB_OUTC
CLKC4
CLKT4
CLKC3
CLKT3
CLKC2