ICS97U2A845A Datasheet, PDF (6/13 Pages) Integrated Circuit Systems – 1.8V Low-Power Wide-Range Frequency Clock Driver

ICS97U2A8 45A
Advance Information
Timing Requirements
T_A = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Max clock frequency
freq_op
1.8V+0.1V @ 25°C
95
Application Frequency Range
freq_App
1.8V+0.1V @ 25°C
160
Input clock duty cycle
d_{t in}
40
CLK stabilization
T_STAB
NOTE: The PLL must be able to handle spread spectrum induced skew.
MAX
410
410
60
15
UNITS
MHz
MHz
%
µs
NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not
required to meet the other timing parameters. (Used for low speed system debug.)
NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters.
NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal, within the value specificied by the Static Phase Offset (t₍Æ ), after power-up. During
normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock
of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode
and later return to active operation. CK and CK may be left floating after they have been driven low for one
complete clock cycle.
Switching Characteristics¹
T_A = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
(MHz)
Output enable time
Output disable time
Period jitter
t_en
t_dis
t_{jit (per)}
OE to any output
OE to any output
160 to 410
160 to 270
271 to 410
Half-period jitter
t_jit(hper)
160 to 270
271 to 410
Input slew rate
SLr1(i)
Input Clock
Output Enable (OE), (OS)
Output clock slew rate
Cycle-to-cycle period jitter
Dynamic Phase Offset
Static Phase Offset
t _{jit (per) +} t _{(Ø)dyn +} t _skew(o)
t_{(Ø)dyn +} t_skew(o)
Output to Output Skew
SLr1(o)
t_jit(cc+)
t_jit(cc-)
t_(Ø)dyn
t_SPO2
∑(su)
∑_{t (h)}
t_skew
160 to 410
160 to 270
271 to 410
271 to 410
160 to 270
271 to 410
SSC modulation frequency
SSC clock input frequency
deviation
PLL Loop bandwidth (-3 dB
from unity gain)
MIN
-40
-30
-60
-50
1
0.5
1.5
0
0
-50
-20
-50
30.00
0.00
2.0
TYP
4.73
5.82
2.5
2.5
0
MAX
8
8
40
30
60
50
4
3
40
-40
50
20
50
80
60
40
30
33
-0.50
UNITS
ns
ns
ps
ps
ps
ps
v/ns
v/ns
v/ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
kHz
%
MHz
1202—06/30/06
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