ICS954101 Datasheet, PDF (6/16 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Desktop P4 Systems

Integrated
Circuit
Systems, Inc.
ICS954101
Absolute Max
Symbol
Parameter
VDD_A
3.3V Core Supply Voltage
VDD_In 3.3V Logic Input Supply Voltage
Ts
Tambient
Tcase
ESD prot
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
GND - 0.5
-65
0
2000
Max
V_DD + 0.5V
V_DD + 0.5V
150
70
115
Units
V
V
°_C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Low Threshold Input High
Voltage
Low Threshold Input Low
Voltage
V_IH
V_IL
I_IH
I_IL1
I_IL2
V_{IH_FS}
V_{IL_FS}
3.3 V +/-5%
3.3 V +/-5%
V_IN = V_DD
V_IN = 0 V; Inputs with no pull-up
resistors
V_IN = 0 V; Inputs with pull-up
resistors
2
V_SS - 0.3
-5
-5
-200
3.3 V +/-5%
0.7
3.3 V +/-5%
V_SS - 0.3
V_DD + 0.3 V
0.8
V
5
uA
uA
uA
V_DD + 0.3 V
0.35
V
Operating Supply Current
I_DD3.3OP
3.3 V +/-5%, Full Load
350
500
mA
Powerdown Current
I_DD3.3PD
all diff pairs driven
all differential pairs tri-stated
70
mA
12
mA
Input Frequency³
F_i
Pin Inductance¹
L_pin
V_DD = 3.3 V
14.31818
7
MHz 3
nH
1
Input Capacitance¹
C_IN
C_OUT
Logic Inputs
Output pin capacitance
5
pF
1
6
pF
1
C_INX
X1 & X2 pins
5
pF
1
Clk Stabilization^1,2
T_STAB
From V_DD Power-Up or de-
assertion of PD# to 1st clock
1.8
ms 1,2
Modulation Frequency
Triangular Modulation
30
33
kHz
1
Tdrive_PD#
CPU output enable after
PD# de-assertion
300
us
1
Tfall_Pd#
PD# fall time of
5
ns
1
Trise_Pd#
PD# rise time of
5
ns
2
SMBus Voltage
V_DD
2.7
5.5
V
1
Low-level Output Voltage
V_OLSMBUS @ I_PULLUP
0.4
V
1
Current sinking at V_OL = 0.4 V I_PULLUP
4
mA
1
SCLK/SDATA
Clock/Data Rise Time
T_RI2C (Max VIL - 0.15) to (Min VIH + 0.15)
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
T_FI2C (Min VIH + 0.15) to (Max VIL - 0.15)
300
ns
1
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{See timing diagrams for timing requirements.}
3 _{Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet• ppm accuracy on PLL outputs.}
0815D—06/21/04
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