ICS954101 Datasheet, PDF (3/16 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Desktop P4 Systems

Integrated
Circuit
Systems, Inc.
ICS954101
Pin Description (Continued)
Pin #
29
30
31
32
33
34
PIN NAME
GND
SRCCLKC5
SRCCLKT5
SRCCLKC6
SRCCLKT6
VDDSRC
35
CPUCLKC2_ITP/SRCCLKC_7
36
CPUCLKT2_ITP/SRCCLKT_7
37
VDDA
38
GNDA
39
IREF
40
CPUCLKC1
41
CPUCLKT1
42
VDDCPU
43
CPUCLKC0
44
CPUCLKT0
45
GND
46
SCLK
47
SDATA
48
VDDREF
49
X2
50
X1
51
GND
52
REFOUT
53
FS_C/TEST_SEL
54
PCICLK0
55
PCICLK1
56
PCICLK2
TYPE
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
PWR
PWR
OUT
DESCRIPTION
Ground pin.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
Complimentary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC
output. These are current mode outputs. External resistors are required
for voltage bias. Selected by ITP_EN input.
True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These
are current mode outputs. External resistors are required for voltage bias.
Selected by ITP_EN input.
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
OUT
OUT
PWR
OUT
OUT
PWR
IN
I/O
PWR
OUT
IN
PWR
OUT
IN
OUT
OUT
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
Reference Clock output
3.3V tolerant input for CPU frequency selection. Low voltage threshold
inputs, see input electrical characteristics for Vil_FS and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
PCI clock output.
PCI clock output.
PCI clock output.
0815D—06/21/04
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