ICS9250-14 Datasheet, PDF (6/13 Pages) Integrated Circuit Systems – Frequency Timing Generator for Pentium II Systems

ICS9250 - 14
Preliminary Product Preview
Byte 0: Functionality and frequency select register (Default=0)
(1 = enable, 0 = disable)
Bit
Bit
(2, 7:4)
Bit 3
Bit 1
Bit 0
Description
Bit (2,7:4)
CPUCLK
MHz
SDRAM
MHz
00000
67.81
101.71
0 0 0 0 1 70.00
105.00
000 10
72.01
108.01
0 0 0 1 1 66.67
100.00
0 0 10 0
73.01
109.51
0 0 1 0 1 75.00
112.50
00 110
77.00
115.50
0 0 1 1 1 78.01
117.01
0 1000
80.00
120.00
0 1 0 0 1 83.00
124.51
0 10 10
84.49
0 1 0 1 1 100.00
0 1 10 0
86.08
126.74
150.00
129.12
0 1 1 0 1 88.00
132.00
0 1110
90.00
135.00
0 1 1 1 1 95.00
142.50
10 00 0
49.90
49.90
1 0 0 0 1 100.00
100.00
100 10
74.85
74.85
1 0 0 1 1 66.58
66.58
10 10 0
82.84
82.84
1 0 1 0 1 89.81
89.81
10 110
94.80
94.80
1 0 1 1 1 100.50
100.50
1 1 0 0 0 104.78
104.78
1 1 0 0 1 111.77
111.77
1 1 0 1 0 114.77
114.77
1 1 0 1 1 100.00
100.00
1 1 1 0 0 123.75
123.75
1 1 1 0 1 132.74
132.74
1 1 1 1 0 139.75
139.75
1 1 1 1 1 149.69
149.69
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,6:4
0- Normal
1- Spread spectrum enable ± 0.25% Center Spread
0- Running
1- Tristate all outputs
3V66
MHz
67.81
70.00
72.01
66.67
73.01
75.00
77.00
78.01
80.00
83.00
84.49
100.00
86.08
88.00
90.00
95.00
33.26
66.66
49.90
44.39
55.23
59.88
63.20
67.00
69.86
74.52
76.51
66.66
82.50
88.49
93.16
99.79
PCICLK
33.90
35.00
36.00
33.33
36.50
37.50
38.50
39.00
40.00
41.50
42.25
50.00
43.04
44.00
45.00
47.50
16.63
33.33
24.95
22.19
27.61
29.94
31.60
33.50
34.93
37.26
38.26
33.33
41.25
44.25
46.58
49.90
IOAPIC
MHz
16.95
17.50
18.00
16.67
18.25
18.75
19.25
19.50
20.00
20.75
21.12
25.00
21.52
22.00
22.50
23.75
8.32
16.67
12.47
11.10
13.81
14.97
15.80
16.75
17.46
18.63
19.13
16.67
20.62
22.12
23.29
24.95
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as diplayed by Bit 3.
PWD
XXXX
Note 1
0
1
0
6