ICS9250-14 Datasheet, PDF (4/13 Pages) Integrated Circuit Systems – Frequency Timing Generator for Pentium II Systems

ICS9250 - 14
Preliminary Product Preview
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
4