ICS9248-77 Datasheet, PDF (6/14 Pages) Integrated Circuit Systems – Frequency Timing Generator for PENTIUM II Systems

ICS9248-77
Serial Configuration Command Bitmap
Byte 0: Functionality and frequency select register (Default = 0)
Bit
Description
Bit 7
0 - ±0.25% Center Spread Spectrum
1 - Down Spread Spectrum 0 to -.5%
Bit (2, 6:4) CPUCLK
3V66
3V66_SEL=0 3V66_SEL=1
PCICLK
0000
105
70
70
35
0001
75
64*
75
37.5
0010
100.3
66.6
66.6
33.4
0011
66.8
66.6
66.6
33.4
0100
110
64*
73.3
36.6
0101
115
64*
76.6
38.3
Bit
0110
117
64*
78
39
(2, 6:4) 0111
120
64*
80
40
1000
125
64*
83.3
41.6
1001
127
64*
84.6
42.3
1010
133.3
66.6
66.6
33.3
1011
135
67.5
67.5
33.75
1100
137
68.5
68.5
34.25
1101
140
70
70
35
1110
145
64*
72.5
36.25
1111
150
64*
75
37.5
Bit 3
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2, 6:4
Bit 1
0 - Normal
1 - Spread spectrum enabled
Bit 0
0 - Running
1 - Tristate all outputs
IOAPIC
FREQ_APIC=0 FREQ_APIC=1
17.5
35
18.75
37.5
16.7
33.4
16.67
33.4
18.3
36.6
19.16
38.3
19.5
39
20
40
20.8
41.6
21.16
42.3
16.6
33.3
16.8
33.75
17.125
34.25
17.5
35
18.125
36.25
18.75
37.5
PWD
0
Note 1
0
0
0
Note 1: Default at power-up will be for latched logic inputs to define frequency.
* These output frequencies are not synchronous to CPUCLK and do not have Spread Spectrum modulation.
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