ICS9179-06 Datasheet, PDF (6/8 Pages) Integrated Circuit Systems – Zero Delay Buffers

ICS9179 - 06
Electrical Characteristics - SDRAM
T_A = 0 - 70C; V_DD = V_DDL = 3.3 V +/-5%; C_L = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output Frequency
F_O3
33
133 MHz
Output Impedance
R_DSP3 V_O = V_DD*(0.5)
10
24 Ohm
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
R_DSN3
V_OH3
V_OL3
I_OH3
V_O = V_DD*(0.5)
I_OH = -30 mA
I_OL = 23 mA
V_OH = 2.0 V
10
24 Ohm
2.6
V
0.4 V
-54 mA
Output Low Current
I_OL3
V_OL = 0.8 V
40
mA
Rise Time
Fall Time
Duty Cycle
Output to Output
Skew Window
IN to FB_IN Skew^{1, 2}
T_r3
T_f3
D_t3
T_sk3
T_skd1
T_skd2
T_skd3
V_OL = 0.4 V, V_OH = 2.4 V
V_OH = 2.4 V, V_OL = 0.4 V
V_T = 1.5 V
V_T = 1.5 V
V_T = 1.5 V default Zero delay I²C
B0 bits 0, 1 = 00
V_T = 1.5 V bits 0, 1 = 10
V_T = 1.5 V bits 0, 1 = 01
1.33 nS
1.33 nS
45
55
%
250 pS
-250 0
250 pS
-2.2 -2.7 -3.2 nS
+1.5 +2.0 +2.5 nS
T_skd4 V_T = 1.5 V bits 0, 1 = 11
-0.2 -0.7 -1.2 nS
Notes:
1. Guarenteed by design, not 100% tested in production
2. Delay elements FBIN and clock INPUT path are selected by I²C BYTE2; bit 0 = clock input control, bit 1 = Clock INPUT
Control. (Default is 0). A 0 = No delay in path, 1 = Delay element selected.
Note: PWD = Power-Up Default
Input Pulse
Input Pulse
Low Time
T_im-Low
Vpulse_Low ≤ 0.8V
Input Pulse
High Time
T_im-High
Vpulse_High ≥ 2.0V
MIN
1.0
1.5
TYP MAX UNITS
ns
ns
6