ICS9179-06 Datasheet, PDF (2/8 Pages) Integrated Circuit Systems – Zero Delay Buffers

ICS9179 - 06
Pin Descriptions
PIN NUMBER
2
5, 6, 9, 10
15, 16, 19, 20
29, 30, 33, 34
40, 41, 44, 45
12
13
24
25
37
3, 7, 11, 17, 21, 31,
35, 38, 42, 46
4, 8, 14, 18, 28, 32,
36, 39, 43, 47
22
23
26
27
1, 48
PIN NAME
OE
OUTPUT (0:3)
OUTPUT (4:7)
OUTPUT (8:11)
OUTPUT (12:15)
INPUT
FB_IN
SDATA
SCLK
FB_OUT
VDD
GND
VDDA
VDDS
GNDS
GNDA
N/C
TYPE
IN
OUT
OUT
OUT
OUT
IN
IN
I/O
I/O
OUT
DESCRIPTION
Tri-states all outputs except FB_OUT when held LOW. Has internal
pull-up.²
SDRAM Byte 0 clock outputs¹
SDRAM Byte 1 clock outputs¹
SDRAM Byte 2 clock outputs¹
SDRAM Byte 3 clock outputs¹
Input for reference clock.
Feedback input.
Data pin for I²C circuitry³
Clock pin for I²C circuitry³
Feedback output to input FB_IN.
PWR 3.3V Power supply for output buffers
PWR Ground for output buffers
PWR
PWR
PWR
PWR
-
3.3V Power supply for Analog PLL stages
3.3V Power supply for I²C circuitry
Ground for I²C circuitry
Ground for Analog PLL stages
Pins are not internally connected
Notes:
1.
At power up all sixteen outputs are enabled and active.
2.
OE has a 100K Ohm internal pull-up resistor to keep all outputs active.
3.
The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for
complete platform flexibility.
4.
I²C Byte0, bits 0 & 1 used to select delay. Default* values at power up is 0
5.
Subject to design engineering verification of target value.
Power Groups
VDD = Power supply for OUTPUT buffers
VDDS = Power supply for I²C circuitry
VDDA = Power supply for Analog PLL circuitry
Ground Groups
GND = Ground supply for OUTPUT buffer
GNDS = Ground supply for I²C circuitry
GNDA = Ground supply for Analog PLL circuitry
Delay Selection Table⁴
INPUT
Control
Byte0 bit1
0*
0
1
1
FB_IN
Control
Byte0 bit0
0*
1
0
1
Nominal Target⁵
Delay, INPUT to
FB_IN pins.
0ns
-2.7ns
+2.0ns
-0.7ns
2