ICS9178-03 Datasheet, PDF (6/8 Pages) Integrated Circuit Systems – 245 MHz Clock Generator and Integrated Buffer for PowerPC

ICS9178-03
AC Characteristics (continued)
V_DD =+5V ±5%, 0°C ≥ TAMBIENT ≥ +70°C unless otherwise stated
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
MAX UNITS
Jitter Absolute 2XPCLK (Note 1)
Tjabs4
for 200 to 240 MHz on
2XPCLK at VDD 4.9 to
5.2V
-125
80
+125
ps
Jitter Absolute 1XPCLK, B, D clocks
(Note 1)
Tjabs5
for 200 to 240 MHz on
2XPCLK at VDD 4.9 to
5.2V
-160
110
+160
ps
Jitter Absolute 2XPCLK (Note 1)
Tjabs6 for < 200 MHz on 2XPCLK -200
-
+200
ps
Jitter Absolute 1XPCLK (Note 1)
Tjabs7 for < 200 MHz on 2XPCLK -250
-
+250
ps
Jitter Absolute AB clock (Note 1)
Tjabs8 for < 200 MHz on 2XPCLK -300
-
+300
ps
Skew, output to output (P, B, D , AB abd
XCLKs) (Note 1)
Tskew1 @ 1.4V
-250
-
+250
ps
Skew, 2XPCLK to PCLK (2XPCLK is
earlier than PCLK) (Note 1)
Tskew2 @ 1.4V
-600
-300
0
ps
Skew, 2XPCLK to REFCLK (2XPCLK is
earlier) (Note 1)
Tskew3
for 240 MHz on 2XPCLK
@ 1.4V
-600
-300
0
ps
Skew, 2XPCLK to DCLK (Notes 1,3)
Tskew4 @ 1.4V
-600
-100
100
ps
Note 1: Parameter is guaranteed by design and characterization. Not tested 100% in production.
Note 2: For 70Ω Load, 2XPCLK level may be pulled-up with a 390Ω resistor to meet minimum pulse width requirements
at both 1.8Vand 0.6Vat 240 Mhz.
Note 3: 2XPCLK is normally earlier than DCLK by up to 600ps and can be later by up to
6