ICS9178-03 Datasheet, PDF (2/8 Pages) Integrated Circuit Systems – 245 MHz Clock Generator and Integrated Buffer for PowerPC

ICS9178-03
Pin Configuration
44-Pin PQFP
X_S1
0
0
1
1
_=A,B,C
X_S0
0
1
0
1
XCLK_(0,1)
PCLK
BCLK
DCLK
Tristate
Functionality
FS1
FS0
RST
0
0
1
0
1
1
1
0
1
1
1
1
X
X
0
0
0
1
0
1
1
1
0
1
1
1
1
TEN
*VCO 2XPCLK PCLK
ABCLK (H/L%)
BCLK DCLK
0
6x REF VCO VCO/2
VCO/6 (66/33)
VCO/6 VCO/4
0
8x REF VCO VCO/2
VCO/8 (75/25)
VCO/8 VCO/4
0
4x REF VCO VCO/2
VCO/12 (50/50)
VCO/4 VCO/4
0
X
1
1
1
1
1
X
X
0
0
0
0
0
1
TCLK TCLK TCLK/2 TCLK/6 (66/33) TCLK/6 TCLK/4
1
TCLK TCLK TCLK/2 TCLK/8 (75/25) TCLK/8 TCLK/4
1
TCLK TCLK TCLK/2 TCLK/12 ( 66/33) TCLK/12 TCLK/4
1
TCLK TCLK TCLK/2
TCLK/2
TCLK/2 TCLK/4
*VCO range is limited from 75- 245 MHz at 5V ±5% and 60 - 170 MHz at 3.3V ±5%. Divide ratios assume BCLK is externally
fed back to FBCLK.
The 2XPCLK series or Thevinen trace terminations must be optimized for the specific operating frequency and board
layout. The rising edge of ABCLK is coincident with the rising edges of 2XPCLK, PCLK and other BCLKs.
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