ICS843011C Datasheet, PDF (6/11 Pages) Integrated Circuit Systems – FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843011C
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
APPLICATION SCHEMATIC
Figure 3A shows a schematic example of the ICS843011C.
An example of LVEPCL termination is shown in this sche-
matic. Additional LVPECL termination approaches are shown
in the LVPECL Termination Application Note. In this example,
an 18 pF parallel resonant 26.5625MHz crystal is used for
generating 106.25MHz output frequency. The C1 = 27pF and
C2 = 33pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 values may be slightly
adjusted for optimizing frequency accuracy.
VCC
R2
10 C3
10uF
VCCA
C4
0. 1u
C2
33pF
XTAL_OUT
X1
26.5625MHz
18pF
XTAL_IN
C1
27pF
U2
1
2
VCCA
3
4
VEE
XTAL_OUT
XTAL_IN
VCC
8
7
Q
nQ
nc
6
5
843011C
VCC
Q
VCC
R3
133
Zo = 50 Ohm
Zo = 50 Ohm
nQ
C5
0.1u
R4
82.5
R5
133
+
-
R6
82.5
Zo = 50 Ohm
Q
Zo = 50 Ohm
nQ
R5
50
+
-
R6
50
Optional
R7
Y-Termination
50
FIGURE 3A. ICS843011C SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of ICS843011C P.C. board lay-
out. The crystal X1 footprint shown in this example allows
installation of either surface mount HC49S or through-hole
HC49 package. The footprints of other components in this
example are listed in the Table 6. There should be at least one
decoupling capacitor per power pin. The decoupling capaci-
tors should be located as close as possible to the power pins.
The layout assumes that the board has clean analog power
ground plane.
TABLE 6. FOOTPRINT TABLE
Reference
Size
C1, C2
0402
C3
0805
C4, C5
0603
R2
0603
NOTE: Table 6, lists component
sizes shown in this layout example.
FIGURE 3B. ICS843011 PC BOARD LAYOUT EXAMPLE
843011CG
www.icst.com/products/hiperclocks.html
6
REV. A JANUARY 25, 2006