ICS83905I Datasheet, PDF (6/16 Pages) Integrated Circuit Systems – LOW SKEW, 1:6 CRYSTAL INTERFACE-TO LVCMOS/LVTTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
TABLE
6C.
AC
CHARACTERISTICS,
V=
DD
V=
DDO
1.8V±0.2V,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
Using External Crystal
f_MAX
Output Frequency _{Using External Clock}
Source; NOTE 1
10
40
MHz
DC
100
MHz
odc
Output Duty Cycle
47
53
%
tsk(o) Output Skew; NOTE 2, 4
80
ps
tjit(Ø) RMS Phase Jitter (Random)
25MHz @ (Integration
Range: 100Hz-1MHz)
0.27
ps
t_R/ t_F
Output Rise/Fall Time
t_EN
Output Enable Time; ^{ENABLE 1}
NOTE 3
ENABLE 2
20% to 80%
200
900
ps
4
cycles
4
cycles
t_DIS
Output Disable Time; ^{ENABLE 1}
NOTE 3
ENABLE 2
4
cycles
4
cycles
All parameters measured at IJ f_MAX using a crystal input unless noted otherwise.
Terminated at 50Ω to V_DDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6D. AC CHARACTERISTICS, V_DD = 3.3V±5%, V_DDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
Using External Crystal
f_MAX
Output Frequency _{Using External Clock}
Source; NOTE 1
10
40
MHz
DC
100
MHz
odc
Output Duty Cycle
48
52
%
tsk(o) Output Skew; NOTE 2, 4
80
ps
tjit(Ø) RMS Phase Jitter (Random)
25MHz @ (Integration
Range: 100Hz-1MHz)
0.14
ps
t_R/ t_F
Output Rise/Fall Time
t_EN
Output Enable Time; ^{ENABLE 1}
NOTE 3
ENABLE 2
20% to 80%
200
800
ps
4
cycles
4
cycles
t_DIS
Output Disable Time; ^{ENABLE 1}
NOTE 3
ENABLE 2
4
cycles
4
cycles
All parameters measured at IJ f_MAX using a crystal input unless noted otherwise.
Terminated at 50Ω to V_DDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83905AGI
http://www.icst.com/products/hiperclocks.html
6
REV. B MAY 16, 2005