ICS83905I Datasheet, PDF (12/16 Pages) Integrated Circuit Systems – LOW SKEW, 1:6 CRYSTAL INTERFACE-TO LVCMOS/LVTTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
LAYOUT GUIDELINE
Figure 2 shows an example of ICS83905I application schematic.
In this example, the device is operated at V_DD = 3.3V and V_DDO =
3.3V. The decoupling capacitors should be located as close as
possible to the power pins. The input is driven by an 18pF load
resonant quartz crystal. The tuning capacitors (C1, C2) are fairly
accurate, but minor adjustments might be required. For the
LVCMOS output drivers, two termination examples are shown
in the schematic. For additional termination, examples are shown
in the LVCMOS Termination Application Note.
CL = 18 pf
VDDO = 3.3V
VDD = 3.3V
R2
31 Zo = 50 Ohm
C2
15pf
U1
C1
15pF
LVCMOS
ENABLE 2
VDD O
1
2
XTAL_OUT
3
4
ENABLE 2
GND
5
6
BC LK0
VD DO
7 ^BCLK1
8
GND
BC LK2
I CS83905I
XTAL_IN
16
15
ENABLE 1
BCLK5
14
13
VDDO
BCLK4
12
11
GND ₁₀
BCLK3
VDD
9
ENABLE 1
VD D
R3
100
Zo = 50 Ohm
R4
100
LVCMOS
VDD
C3
10uF
C4
. 1uF
VDDO
C5
. 1uF
C6
.1uF
Optional Termination
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
FIGURE 2. Schematic of Recommended Layout
83905AGI
http://www.icst.com/products/hiperclocks.html
12
REV. B MAY 16, 2005