ICSSSTVA16859B Datasheet, PDF (5/11 Pages) Integrated Circuit Systems – DDR 13-Bit to 26-Bit Registered Buffer

ICSSSTVA16859B
DC Electrical Characteristics - DDRI/DDR333 (PC1600, PC2100, PC2700)
T_A = 0 - 70°C; V_DD = 2.5 +/-0.2V, V_DDQ=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL PARAMETERS
CONDITIONS
V_DDQ
MIN
V_IK
I_I = -18mA
2.3V
V_OH
I_OH = -100µA
2.3V-2.7V ^{VDDQ -}
0.2
I_OH = -8mA
2.3V
1.95
V_OL
I_OL = 100µA
I_OL = 8mA
2.3V-2.7V
2.3V
I_I
All Inputs
Standby (Static)
V_I = V_DD or GND
RESET# = GND
2.7V
I_{DD Operating (Static)}
V_I = V_IH(AC) or V_IL(AC),
RESET# = V_DD
RESET# = V_DD,
V_I
Dynamic operating
(clock only)
= V_IH(AC) or V_IL(AC), CLK
and CLK# switching 50%
duty cycle.
I_O = 0
2.7V
I_DDD
RESET# = V_DD,
V_I
= V_IH(AC) or V_{IL (AC)}, CLK
Dynamic Operating and CLK# switching 50%
(per each data input) _{duty cycle. One data input}
switching at half clock
frequency, 50% duty cycle
r_OH Output High
I_OH = -16mA
r_OL Output Low
I_OL = 16mA
r_O(D)
[r_OH - r_OL] each
separate bit
C_i
Data Inputs
CLK and CLK#
I_O = 20mA, T_A = 25° C
V_I = V_REF ±350mV
V_ICR = 1.25V, V_I(PP) = 360mV
Notes:
1 - Guaranteed by design, not 100% tested in production.
2.3V-2.7V
7
2.3V-2.7V
7
2.5V
2.5V
2.5
2.5
TYP
TBD
TBD
TBD
13.5
13
MAX
-1.2
UNITS
V
0.2
0.35
±5
µA
0.01
µA
mA
µ/clock MHz
µA/ clock
MHz/data
20
Ω
20
Ω
4
Ω
3.5
pF
3.5
1050A—01/07/05