ICSSSTVA16859B Datasheet, PDF (1/11 Pages) Integrated Circuit Systems – DDR 13-Bit to 26-Bit Registered Buffer

Integrated
Circuit
Systems, Inc.
ICSSSTVA16859B
DDR 13-Bit to 26-Bit Registered Buffer
Recommended Applications:
• DDR Memory Modules:
- DDRI (PC1600, PC2100)
- DDR333 (PC2700)
- DDRI-400 (PC3200)
• Provides complete DDR DIMM solution with
ICS93V857 or ICS95V857
• SSTL_2 compatible data registers
Product Features:
• Differential clock signals
• Meets SSTL_2 signal data
• Supports SSTL_2 class I specifications on outputs
• Low-voltage operation
- V_DD = 2.3V to 2.7V
• Available in 64 pin TSSOP and 56 pin MLF packages
• Exceeds SSTVN16859 performance
Truth Table¹
Inputs
RESET# CLK
CLK#
L
X or
X or
Floating Floating
H
↑
↓
H
↑
↓
H
L or H L or H
Notes:
D
X or
Floating
H
L
X
Q Outputs
Q
L
H
L
Q₀₍₂₎
Pin Configurations
Q13A
1
Q12A
2
Q11A
3
Q10A
4
Q9A
5
VDDQ
6
GND
7
Q8A
8
Q7A
9
Q6A
10
Q5A
11
Q4A
12
Q3A
13
Q2A
14
GND
15
Q1A
16
Q13B
17
VDDQ
18
Q12B
19
Q11B
20
Q10B
21
Q9B
22
Q8B
23
Q7B
24
Q6B
25
GND
26
VDDQ
27
Q5B
28
Q4B
29
Q3B
30
Q2B
31
Q1B
32
64
VDDQ
63
GND
62
D13
61
D12
60
VDD
59
VDDQ
58
GND
57
D11
56
D10
55
D9
54
GND
53
D8
52
D7
51
RESET#
50
GND
49
CLK#
48
CLK
47
VDDQ
46
VDD
45
VREF
44
D6
43
GND
42
D5
41
D4
40
D3
39
GND
38
VDDQ
37
VDD
36
D2
35
D1
34
GND
33
VDDQ
64-Pin TSSOP
6.10 mm. Body, 0.50 mm. pitch
1. H = "High" Signal Level
L = "Low" Signal Level
56
43
↑ = Transition "Low"-to-"High"
↓ = Transition "High"-to-"Low"
Q7A ¹
42 D10
X = Don't Care
Q6A
Q5A
2. Output level before the indicated steady state
input conditions were established.
Q4A
Q3A
Block Diagram
Q2A
D9
D8
D7
RESET#
GND
CLK
CLK#
Q1A
Q13B
VDDQ
Q12B
ICSSSTVA16859B
CLK#
CLK
VDDQ
VDD
RESET#
D1
VREF
R
CLK
D1
Q1A
Q1B
Q11B
Q10B
Q9B
Q8B14
VREF
D6
D5
29 D4
15
28
1050A—01/07/05
To 12 Other Channels
56-Pin VFQFN (MLF2)