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ICS9248-87 Datasheet, PDF (5/13 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™
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ICS9248-87
Preliminary Product Preview
Byte 0: Control Register Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved
Bit6 -
0 Reserved
Bit5 -
0 Reserved
Bit4 -
0 Reserved
Bit3 -
0 Reserved
Bit2 23 1 24/48MHz
Bit1 21,22 1 48MHz
Bit0 -
0 Reserved
Byte 1: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 32
1 SDRAM7
Bit6 33
1 SDRAM6
Bit5 35
1 SDRAM5
Bit4 36
1 SDRAM4
Bit3 37
1 SDRAM3
Bit2 39
1 SDRAM2
Bit1 40
1 SDRAM1
Bit0 41
1 SDRAM0
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 19 1 PCICLK7
Bit6 18 1 PCICLK6
Bit5 17 1 PCICLK5
Bit4 15 1 PCICLK4
Bit3 14 1 PCICLK3
Bit2 12 1 PCICLK2
Bit1 11 1 PCICLK1
Bit0 10 1 PCICLK0
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved
Bit6 -
0 Reserved
Bit5 -
0 Reserved
Bit4 -
0 Reserved
Bit3 -
0 Reserved
Bit2 -
0 Reserved
Bit1 -
0 Reserved
Bit0 -
0 Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
3. SDRAM_F is free running and cannot be turned off by I2C
Byte 3: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved
Bit6 -
X FS2#
Bit5 -
X FS1#
Bit4 -
X FS0#
Bit3 -
1 IOAPIC
Bit2 -
Bit1 -
Bit0 -
X (SEL24_48#)#
FREQ_IOAPIC
1
=1=>IOAPIC=PCICLK/2
FREQ_IOAPIC=0=>
IOAPIC= PCICLK
X FS3#
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved (Note)
Bit6 -
0 Reserved (Note)
Bit5 -
0 Reserved (Note)
Bit4 -
0 Reserved (Note)
Bit3 -
0 Reserved (Note)
Bit2 -
1 Reserved (Note)
Bit1 -
1 Reserved (Note)
Bit0 -
0 Reserved (Note)
Note: Don’t write into this register, writing into this
register can cause malfunction
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