ICS9248-87 Datasheet, PDF (2/13 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9248-87
Preliminary Product Preview
General Description
The ICS9248-87 is the single chip clock solution for designs
using 810/810E style chipset. It provides all necessary clock
signals for such a system.
Spread spectrum may be enabled through I²C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-87
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I²C interface allows changing functions,
stop clock programming and frequency selection.
Power Groups
GNDREF, VDDREF = REF1, X1, X2
GNDPCI, VDDPCI = PCICLK [7:0]
GNDSDRAM, VDDSDRAM = SDRAM [8:0]
GND3V66, VDD3V66 = 3V66
VDD48 = 48MHz, 24MHz
GNDCOR, VDDCOR = supply for PLL core
VDDLAPIC = IOAPIC
GNDLCPU, VDDLCPU = CPUCLKL [1:0]
Pin Configuration
PIN NUMBER
1
2, 6, 16, 24, 27, 34,
42
3
4
5, 9, 13, 20, 26, 30,
38
8, 7
10
11
12
19, 18, 17, 15, 14
21, 22
PIN NAME
REF1
FS3
VDD
X1
X2
GND
3V66 [1:0]
FS0
PCICLK0
FS1
PCICLK1
FS2
PCICLK2
PCICLK [7:3]
48MHz
23
SEL24_48#
24_48MHz
25
SDATA
28
SCLK
29
PD#
31
32, 33, 35, 36, 37,
39, 40, 41
43
44, 45
46
47
48
SDRAM_F
SDRAM [7:0]
GNDLCPU
CPUCLK [1:0]
VDDLCPU
IOAPIC
VDDLAPIC
TYPE
OUT
IN
PWR
IN
OUT
PWR
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
IN
IN
OUT
OUT
PWR
OUT
PWR
OUT
PWR
DESCRIPTION
14.318 MHz reference clock.
Frequency select pin.
3.3V Power supply for SDRAM output buffers, PCI output buffers, reference
output buffers and 48MHz output
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Ground pin for 3V outputs.
3V66 clock outputs.
Frequency select pin.
PCI clock output.
Frequency select pin.
PCI clock output.
Frequency select pin.
PCI clock output.
PCI clock outputs.
48MHz output clocks
Sel pin for enabling 24MHz or 48MHz
H=24MHz L=48MHz
Clock output for super I/O/USB
Data input for I2C serial input, 5V tolerant input
Clock input of I2C input, 5V tolerant input
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
SDRAM clock output - free running not affected by I²C
SDRAM clock outputs
Ground pin for the CPU clocks.
CPU clock outputs.
Power pin for the CPUCLKs. 2.5V
2.5V clock output
Power pin for the IOAPIC. 2.5V
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