ICS9248-73 Datasheet, PDF (5/15 Pages) Integrated Circuit Systems – Frequency Timing Generator for Pentium II Systems

ICS9248 - 73
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
-
X
-
X
-
X
28
1
27
1
26
1
-
0
31
1
Description
FS3#
FS0#
FS2#
24-48MHz
48MHz
48MHz
(Reserved)
SDRAM_F
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
32
1
33
1
35
1
36
1
37
1
39
1
40
1
41
1
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 3: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
20
1
19
1
17
1
16
1
15
1
13
1
12
1
11
1
Description
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Byte 4: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
-
0
7
1
8
1
-
X
47
1
-
X
44
1
45
1
Description
(Reserved)
3V66_0
3V66_1
SEL_3V66#
IOAPIC
FS1#
CPUCLK1
CPUCLK0
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured
at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
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