ICS9248-73 Datasheet, PDF (4/15 Pages) Integrated Circuit Systems – Frequency Timing Generator for Pentium II Systems

ICS9248 - 73
Byte 0: Functionality and frequency select register (Default=0)
(1 = enable, 0 = disable)
Bit
Bit 7
Description
0 - ±0.25% Center Sperad Spectrum
1-Down Spread Spectrum 0 to -0.5%
Bit
(2, 6:4)
Bit 3
Bit 1
Bit 0
Bit CPUCLK SDRAM PCICLK
3V66 MHz
(2, 6:4) MHz
MHz
MHz
SEL_3V66=0 SEL_3V66=1
0000 100.23 100.23 33.41
66.82
66.82
0001 100.90 100.90 33.63
67.26
67.26
0010 105.00 105.00 35.00
70.00
70.00
0011 66.89 100.33 33.44
66.89
66.89
0100 120.00 120.00 40.00
64.00*
80.00
0101 124.00 124.00 41.33
64.00*
82.66
0110 133.30 133.30 44.43
64.00*
88.86
0111 133.30 133.30 33.32
66.65
66.65
1000 140.00 140.00 35.00
70.00
70.00
1001 150.00 150.00 37.50
64.00*
75.00
1010 114.99 114.99 38.33
64.00*
76.66
1011 70.00 105.00 35.00
70.00
70.00
1100 75.00 112.50 37.50
64.00*
75.00
1101 83.31 124.96 41.65
64.00*
83.31
1110 90.00 90.00 30.00
60.00
60.00
1111 95.00 95.00 31.67
63.33
63.33
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2, 6:4
0 - Normal
1 - Spread spectrum enable
0 - Running
1 - Tristate all outputs
IOAPIC MHz
16.70
16.81
17.50
16.72
20.00
20.67
22.21
16.66
17.50
18.75
19.16
17.50
18.75
20.83
15.00
15.83
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, Bit 2, 6:4 are default to 0000.
* These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation.
PWD
0
XXXX
Note 1
0
0
0
4