ICS9248-65 Datasheet, PDF (5/10 Pages) Integrated Circuit Systems – Frequency Timing Generator for PENDIUM II Systems

ICS9248-65
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Group Offset
Group
Offset
CPU to 3V66
0.0-1.5ns CPU leads
3V66 to PCI
1.5-4.0ns 3V66 leads
CPU to IOAPIC
1.5-4.0ns CPU leads
No te: 1 . All o ffsets are to be meas u red at ris in g edg es.
Measurement Loads
CPU @ 20pF, 3V66 @ 30pF
3V66 @ 30pF, PCI @ 30pF
CPU @ 20pF, IOAPIC @ 20pF
Measure Points
CPU @1.25V, 3V66 @ 1.5V
3V66 @ 1.5V, PCI @ 1.5V
CPU @1.25V, IOAPIC @ 1.5V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = VDDL = 3.3 V +/-5%, (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High Voltage
V_IH
2
V_DD+0.3 V
Input Low Voltage
V_IL
V_SS-0.3
0.8
V
Input High Current
I_IH
V_IN = V_DD
0.1
5
µA
Input Low Current
I_IL1
V_IN = 0 V; Inputs with no pull-up resistors
-5 2.0
µA
Input Low Current
I_IL2
V_IN = 0 V; Inputs with pull-up resistors
-200 -100
µA
IDD3.3OP100 CL = 0 pF; Select @ 100 MHz
65
Operating
IDD3.3OP133 CL = 0 pF; Select @ 133.3 MHz
IDD3.3OP144 CL = 0 pF; Select @ 144 MHz
71
160 mA
75
Power Down
IDD3.3OP154 CL = 0 pF; Select @ 154 MHz
IDD3.3PD CL = 0 pF; PWRDWN# = 0
78
64 200 µA
Supply Current
Input frequency
Input Capacitance¹
Transition Time¹
Settling Time¹
Clk Stabilization¹
Skew¹
Skew¹
Skew¹
F_i
C_IN
C_INX
T_trans
T_s
T_STAB
tCP U -P CI
tCP U -3 V6 6
t3 V6 6 -P CI
V_DD = 3.3 V
Logic Inputs
X1 & X2 pins
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From V_DD = 3.3 V to 1% target Freq.
VT = 1.5 V; VTL = 1.25 V
VT = 1.5 V; VTL = 1.25 V
VT = 1.5 V
12 14.318 16
5
27
36
45
1
3
0.5
3
1.5 2.4
4
1.4 1.5
1.4
4
MHz
pF
pF
ms
ms
ms
ns
ns
ns
1_{Guaranteed by design, not 100% tested in production.}
5