ICS9248-65 Datasheet, PDF (2/10 Pages) Integrated Circuit Systems – Frequency Timing Generator for PENDIUM II Systems

ICS9248-65
General Description
The ICS9248-65 is a main clock synthesizer chip for Pentium
II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used
with a Direct Rambus Clock Generator(DRCG) chip such as
the ICS9211-01.
Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI by
8dB to 10dB. This simplifies EMI qualification without
resorting to board design iterations or costly shielding. The
ICS9248-65 employs a proprietary closed loop design, which
tightly controls the percentage of spreading over process
and temperature variations.
The CPU/2 clocks are inputs to the DRCG.
Power Groups:
VDDREF, GNDREF = REF, X1, X2
GNDPCI, VDDPCI = PCICLK
VDD66, GND66 = 3V66
VDD48, GND48 = 48MHz
VDDCOR, GNDCOR = PLL Core
VDDLCPU/2 , GNDLCPU/2 = CPU/2
VDDLIOAPIC, GNDIOAPIC = IOAPIC
Pin Descriptions
Pin number Pin name Type
Description
1,2
REF
3, 9, 17, 24,
28, 34
VDD
4
X1
5
X2
6,14, 20, 26,
33, 45, 48
GND
7
PCICLK_F
8,10,11,12,13, _{PCICLK (1:9)}
15,16,18,19
21,22,23
3V66
Output
Power
Input
Output
Power
Output
Output
Output
3.3V, 14.318 MHz reference clock output.
3.3 V power for clock outputs.
14.318 MHz crystal input
14.318 MHz crystal output
Ground for clock outputs
3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
3.3 V PCI clock outputs, generating timing requirements for
3.3 V 66 MHz clock output, fixed frequency clock typically used with AGP
Control for the frequency of clocks at the CPU output pins. If logic "0" is used the
25
SEL
Input 100 MHz frequency is selected. If Logic "1" is used, the 133 MHz frequency is
133/100#
selected. The PCI clock is multiplexed to run at 33.3 MHz for both selected cases.
27
29,30
31
32
35,39
36,37,40
38,41
42
43
44
46
47
48 MHz
SEL (0:1)
SPREAD#
PD#
GNDLCPU
CPUCLK
(0:2)
VDDLCPU
GNDLCPU/2
CPU/2
VDDLCPU/2
IOAPIC(0:1)
VDDIOAPIC
Output
Input
Output
Input
Power
0utput
Power
Power
Output
Power
Output
Power
3.3 V 48 MHz clock output, fixed frequency clock typically used with USB
devices
Frequency select pin , logic input.
Power-on spread spectrum enable option. Active low = spread spectrum clocking
enable. Active high = spread spectrum clocking disable.
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped.
Ground for the CPU and Host clock outputs
2.5 V CPU and Host clock outputs
2.5 V power for the CPU and Host clock outputs
Ground for the CPU and Host clock outputs
Output running at 1/2 CPU clock frequency.Synchronous to the CPU outputs.
2.5 V power for the CPU/2 clock outputs
2.5V fixed 16.6 MHz IOAPIC clock outputs
2.5V power for IOAPIC clock
2