ICS9248-64 Datasheet, PDF (5/15 Pages) Integrated Circuit Systems – AMD-K7TM System Clock Chip

ICS9248-64
Byte 4: Clock Control Register
BIT PIN# PWD
DESCRIPTION
7
1
1 REF0 enable
6
24
1 24MHz/48MHz enable
5
23
1 48MHz enable
4
20
1 AGP1 enable
3
19
1 AGP0 enable
CPUCLK2 enable (both of
2 42, 43 1 differential pair, True" and
"Complimentary"
CPUCLK1 enable (both of
1 39, 40 1 differential pair, True" and
"Complimentary"
CPUCLK0 enable (both of
0 36, 37 1 differential pair, True" and
"Complimentary"
Notes: A value of '1'b is enable, '0'b is disable
Byte 5: PCI Clock Control Register
BIT PIN# PWD
DESCRIPTION
7
2
1 REF1 enable
6
17
1 PCICLK6 enable
5
16
1 PCICLK5 enable
4
14
1 PCICLK4 enable
3
13
1 PCICLK3 enable
2
11
1 PCICLK2 enable
1
10
1 PCICLK1 enable
0
8
1 PCICLK0 enable
Notes: A value of '1'b is enable, '0'b is disable
Byte 6: SDRAM Clock & Generator Mode Control Register
Bit
Description
PWD
7
Spread Spectrum enable down spread
1
Bit
654
CPU
PCI Spread Percentage
111 100
33.3 1% Down Spread
110 120
30 1% Down Spread
6:4
101
100
133
90
33.3 1% Down Spread
30 -0.5%Down Spread
011 TCLK/2 TCLK/6 1% Down Spread
1
010 66
33 -0.5%Down Spread
001 50
25 1% Down Spread
000 HI-Z
HI-Z 1% Down Spread
2:3
(Reserved)
1
1 I²C enable
1
0 SDRAM_OUT Enable
1
Notes: A value of '1'b is enable, '0'b is disable
5