ICS9248-64 Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – AMD-K7TM System Clock Chip

ICS9248-64
Pin Descriptions
PIN NUMBER
1, 2
3
4
5
6, 12
7
8, 10, 11, 13,
14,16,17
9, 15
18
19, 20
21
22
23
24
25
26
27
28
PIN NAME
FS(0:1)
REF(0:1)
GNDREF
X1
X2
GNDPCI
PCICLK_F
PCICLK (0:6)
VDDPCI
VDDAGP
AGP (0:1)
GNDAGP
VDD48
48MHz
SEL24-48#
24-48MHz
GND48
SCLK
SDATA
TEST#
29
SPREAD#
30
PD#
31
CPU_STOP#
32
33
34
35, 44
36, 39, 42,
37, 40, 43
38, 41
45
46
47
48
PCI_STOP#
GND
VDD
RESERVED
CPUCLKT (0:2)
CPUCLKC(0:2)
GNDCPU
VDDSD
SDRAM_OUT
GNDSD
VDDREF
TYPE
IN
OUT
PWR
IN
OUT
PWR
OUT
OUT
PWR
PWR
OUT
PWR
PWR
OUT
IN
OUT
PWR
IN
IN
IN
IN
IN
IN
IN
PWR
PWR
N/C
OUT
OUT
PWR
PWR
OUT
PWR
PWR
DESCRIPTION
Frequency Select pins, has pull-up to VDD
14.318MHz clock output
Ground for REF outputs
XTAL_IN 14.318MHz Crystal input, has internal 33pF load
cap and feed back resistor from X2
XTAL_OUT Crystal output, has internal load cap 33pF
Ground for PCI outputs
Free Running PCI output. Not affected by the PCI_STOP#
input.
PCI clock outputs. TTL compatible 3.3V
Power for PCICLK outputs, nominally 3.3V
Power for AGP outputs, nominally 3.3V
AGP outputs defined as 2X PCI. These may not be stopped.
Ground for AGP clock outputs
Power for USB, FDC outputs nominally 3.3V
48MHz output
Selects 24 or 48MHz output for pin 24
Low = 48MHz High = 24MHz
Fixed clock out selectable through SEL24-48#
Ground for 48MHz outputs
Clock input for I²C
Data input for I²C
Tri State or test mode when low
(please refer to frequency table)
Enables Spread Spectrum feature when LOW. Down Spread
0.5% modulation frequency =50KHz
Powers down chip, active low. Internal PLL & all outputs are
disabled.
Halts CPUCLKs. CPUCLKT(0:2) is driven LOW whereas
CPUCLKC(0:2) is driven HIGH when this pin is asserted
(Active LOW).
Halts PCI Bus at logic "0" level when driven low. PCICLK_F
is not affected by this pin
Isolated ground for core
Isolated power for core, nominally 3.3V
Furture CPU power rail
"True" clocks of differential pair CPU outputs. These open
drain outputs need an external 1.5V pull-up.
"Complementory" clocks of differental pair CPU output. These
open drain outputs need an external 1.5V pull_up.
Ground for CPUCLK outputs.
Power for SDRAM_OUT pin. Norminally 3.3V
Reference clock for SDRAM zero delay buffer
Ground for SDRAM_OUT pins
Power for REF (0:1), X1, X2, nominally 3.3V
2