ICS9248-168 Datasheet, PDF (5/14 Pages) Integrated Circuit Systems – AMD - K7™ Clock Generator for Mobile System

ICS9248-168
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
22
5
4
42
-
41, 40
-
42
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
FS0
FS1
FS2
CPUCLK 0=1.5X 1=1X
Reserved
CPUCLKT/C 0=1.5X 1=1X
Reserved
CPUCLK
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
4
15
12
11
10
9
8
5
PWD
DESCRIPTION
1 PCICLK_F
1 PCICLK6
1 PCICLK5
1 PCICLK4
1 PCICLK3
1 PCICLK2
1 PCICLK1
1 PCICLK0
Byte 3: Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
23
22
23
48
47
46
-
PWD
DESCRIPTION
1 Reserved
1 SEL24_48#
1 48MHz
1 24_48MHz
1 REF0
1 REF1
1 REF2
1 Reserved
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
27
28
29
32
33
36
37
PWD
DESCRIPTION
1 Reserved
1 SDRAM_F
1 SDRAM5
1 SDRAM4
1 SDRAM3
1 SDRAM2
1 SDRAM1
1 SDRAM0
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
-
1 Reserved
-
1 Reserved
-
1 Reserved
-
1 Reserved
-
1 Reserved
-
1 Reserved
-
1 Reserved
-
1 Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7 -
0 Reserved
Bit 6 -
0 Reserved
Bit 5 -
0 Reserved
Bit 4 -
0 Reserved
Bit 3 -
0 Reserved
Bit 2 -
1 Reserved
Bit 1 -
1 Reserved
Bit 0 -
0 Reserved
Note: Don’t write into this register, writing into this
register can cause malfunction
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