ICS9248-168 Datasheet, PDF (2/14 Pages) Integrated Circuit Systems – AMD - K7™ Clock Generator for Mobile System

ICS9248-168
Pin Descriptions
PIN NUMBER
1, 6, 14, 24,
30, 35, 43
PIN NAME
VDD
2
X1
3
X2
FS2^{1, 2}
4
PCICLK_F
5
7, 13, 20, 21, 31, 34,
44, 45
15, 12, 11, 10, 9, 8
FS1^{1, 2}
PCICLK0
GND
PCICLK (6:1)
16
SDRAM_STOP#
17
PCICLK_STOP#
18
BUFFER IN
19
AVDD
FS0^{1, 2}
22
48MHz
SEL24_48#^{1, 2}
23
24_48MHz
25
SDATA
26
SCLK
27
SDRAM_F
28, 29, 32, 33, 36, 37 SDRAM (5:0)
38
PD#
39
CPU_STOP#^1,
40
CPUCLKC0
41
42
46, 47, 48
CPUCLKT0
CPUCLK
REF0 (2:0)
TYPE
DESCRIPTION
PWR Power supply, nominal 3.3V
IN
OUT
IN
OUT
IN
OUT
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
Frequency select pin. Latched Input. Internal Pull-up to VDD
Free running PCI clock not affected by PCI_STOP# for power
management.
Frequency select pin. Latched Input. Internal Pull-up to VDD
PCI clock output
PWR Ground
OUT
IN
IN
IN
PWR
IN
OUT
IN
OUT
I/O
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
PCI clock outputs.
Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level,
when input low
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low
Input to Fanout Buffers for SDRAM outputs.
Supply for core, & CPU 3.3V
Frequency select pin. Latched Input
48MHz output clock
Logic input to select 24 or 48MHz for pin 25 output
24MHz/48MHz clock output
Data pin for I²C circuitry 5V tolerant
Clock pin of I²C circuitry 5V tolerant
Free running SDRAM clock not affected by SDRAM_STOP# for
power management.
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
Powers down chip, active low
This asynchronous input halts CPUCLKT, CPUCLKC & SDRAM at
logic "0" level when driven low.
"Complementory" clock of differential pair CPU output. This open
drain outputs needs an external 1.5V pull-up.
"True" clocks of differential pair CPU outputs. These open drain
outputs need an external 1.5V pull-up.
3.3V CPU clock output powered by VDDA
14.318 Mhz reference clock.
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
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