ICS9248-126 Datasheet, PDF (5/12 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™ & K6

ICS9248-126
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
43
45
46
-
PWD
DESCRIPTION
SEL24_48#
1 (48MHz when set to 0)
(24MHz when set to 1)
1 Reserved
1 Reserved
1 Reserved
1 CPUCLK2 (Act/Inact)
1 CPUCLK1 (Act/Inact)
1 CPUCLK0 (Act/Inact)
1 Reserved
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
14
13
12
11
9
8
7
PWD
DESCRIPTION
1 (CPU2.5_3.3#)
1 PCICLK6 (Act/Inact)
1 PCICLK5 (Act/Inact)
1 PCICLK4 (Act/Inact)
1 PCICLK3 (Act/Inact)
1 PCICLK2 (Act/Inact)
1 PCICLK1 (Act/Inact)
1 PCICLK0 (Act/Inact)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
32
31
29
28
21
20
18
17
PWD
DESCRIPTION
1 SDRAM 7 (Act/Inact)
1 SDRAM 6 (Act/Inact)
1 SDRAM 5 (Act/Inact)
1 SDRAM 4 (Act/Inact)
1 SDRAM 3 (Act/Inact)
1 SDRAM 2 (Act/Inact)
1 SDRAM 1 (Act/Inact)
1 SDRAM 0 (Act/Inact)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
25
26
41
40
38
37
35
34
PWD
DESCRIPTION
1 24_48MHz
1 48MHz
1 SDRAM13
1 SDRAM12
1 SDRAM11
1 SDRAM10
1 SDRAM9
1 SDRAM8
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
48
2
PWD
DESCRIPTION
1 Reserved
1 Reserved
1 FS3#
1 FS2#
1 FS1#
1 FS0#
1 REF1 (Act/Inact)
1 REF0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved (Note)
Bit6 -
0 Reserved (Note)
Bit5 -
0 Reserved (Note)
Bit4 -
0 Reserved (Note)
Bit3 -
0 Reserved (Note)
Bit2 -
1 Reserved (Note)
Bit1 -
1 Reserved (Note)
Bit0 -
0 Reserved (Note)
Note: Don’t write into this register, writing into this
register can cause malfunction
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