ICS9248-126 Datasheet, PDF (11/12 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™ & K6

ICS9248-126
General Layout Precautions:
1) Use a ground plane on the top routing
layer of the PCB in all areas not used
VDD
by traces.
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.
Notes:
1 All clock outputs should have
provisions for a 15pf capacitor
between the clock output and series
terminating resistor. Not shown in all
places to improve readability of
diagram.
2 Optional crystal load capacitors are
recommended. They should be
included in the layout but not
inserted unless needed.
Component Values:
C1 : Crystal load values determined by user
C2 : 22µF/20V/D case/Tantalum
AVX TAJD226M020R
C3 : 15pF capacitor
FB = Fair-Rite products 2512066017X1
All unmarked capacitors are 0.01µF ceramic
Ferrite
Bead
C1
C1
2
3.3V Power Route
C2
22µF/20V
Tantalum
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C2
22µF/20V
Tantalum
Ferrite
Bead
VDD
48
47
46
45
C3
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2.5V Power Route
C3
1
Clock Load
Ground
3.3V Power Route
Connections to VDD:
= Routed Power
= Ground Connection Key (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
= Clock Load
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