ICS9248-112 Datasheet, PDF (5/12 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9248-112
Preliminary Product Preview
Byte 1: Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
27
-
26
-
30
PWD
DESCRIPTION
X FS3#
X FS0#
X FS2#
1 24MHz
1 (Reserved)
1 48MHz
1 (Reserved)
1 SDRAM_F
Byte 3: PCI, Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
20
19
17
16
15
13
12
11
PWD
DESCRIPTION
1 PCICLK7
1 PCICLK6
1 PCICLK5
1 PCICLK4
1 PCICLK3
1 PCICLK2
1 PCICLK1
1 PCICLK0
Byte 2: SDRAM, Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7 31 1 SDRAM7
Bit 6 32
1 SDRAM6
Bit 5 34
1 SDRAM5
Bit 4 35
1 SDRAM4
Bit 3 36
1 SDRAM3
Bit 2 38
1 SDRAM2
Bit 1 39
1 SDRAM1
Bit 0 40
1 SDRAM0
Byte 4: Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7 -
0 (Reserved)
Bit 6 8
1 3V66_1
Bit 5 7
1 3V66_0
Bit 4 -
X FREQ_IOAPIC#
Bit 3 46
1 IOAPIC
Bit 2 -
X FS1#
Bit 1 43
1 CPUCLK1
Bit 0 44
1 CPUCLK0
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
1 Reserved
Bit6 -
1 Reserved
Bit5 -
1 Reserved
Bit4 -
1 Reserved
Bit3 -
1 Reserved
Bit2 -
1 Reserved
Bit1 -
1 Reserved
Bit0 -
1 Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved (Note)
Bit6 -
0 Reserved (Note)
Bit5 -
0 Reserved (Note)
Bit4 -
0 Reserved (Note)
Bit3 -
0 Reserved (Note)
Bit2 -
1 Reserved (Note)
Bit1 -
1 Reserved (Note)
Bit0 -
0 Reserved (Note)
Note: Don’t write into this register, writing into this
register can cause malfunction
Third party brands and names are the property of their respective owners.
5