ICS9248-112 Datasheet, PDF (2/12 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9248-112
Preliminary Product Preview
General Description
The ICS9248-112 is the single chip clock solution for designs
using the 810/810E style chipset. It provides all necessary
clock signals for such a system.
Spread spectrum may be enabled through I²C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-112
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I²C interface allows changing functions,
stop clock programming and frequency selection.
Power Groups
GNDREF, VDDREF = REF0, X1, X2
GNDPCI , VDDPCI = PCICLK [9:0]
GNDSDR, VDDSDR = SDRAM [7:0], SDRAM_F,
supply for PLL core
GND3V66 , VDD3V66 = 3V66
GND48 , VDD48 = 48MHz, 24_48MHz,
VDDLAPIC = IOAPIC
GNDLCPU , VDDLCPU = CPUCLK [1:0]
Pin Configuration
PIN
NUMBER
1
2, 9, 10, 18,
25, 29, 37
3
PIN NAME
REF1
VDD
X1
4
X2
5, 6, 14, 21, 28,
33, 41
GND
7, 8
3V66 (1:0)
PCICLK0¹
11
FS0
PCICLK1¹
12
FS1
13, 15, 16,
17, 19, 20
PCICLK (2:7)
22
PD#
23
SCLK
24
SDATA
48MHz
26
FS3
27
30
40, 39, 38, 36,
35, 34, 32, 31
42
FS2
24MHz
SDRAM_F
SDRAM (7:0)
GNDL
43, 44
CPUCLK (1:0)
45, 47
46
48
VDDL
IOAPIC
REF0¹
FREQ_IOAPIC
TYPE
DESCRIPTION
OUT 3.3V, 14.318MHz reference clock output.
PWR 3.3V power supply
IN
OUT
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
PWR Ground pins for 3.3V supply
OUT
OUT
IN
OUT
IN
3.3V clock outputs for HUB running at 2XPCI MHz
3.3V PCI clock outputs, with Synchronous CPUCLKS
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock outputs, with Synchronous CPUCLKS
Logic input frequency select bit. Input latched at power on.
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
Asynchronous active low input pin used to power down the device into
IN
a low power state. The internal clocks are disabled and the VCO and
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
IN Clock input of I²C input
IN Data input for I²C serial input.
OUT 3.3V Fixed 48MHz clock output for USB
IN Logic input frequency select bit. Input latched at power on.
IN Logic input frequency select bit. Input latched at power on.
OUT 3.3V fixed 24MHz output
OUT 3.3V free running SDRAM not affected by I²C
OUT 3.3V outputs
PWR
OUT
PWR
OUT
OUT
IN
Ground for 2.5V power supply for CPU & APIC
2.5V Host bus clock output.
2.5V power supply for CPU, IOAPIC
2.5V clock output
3.3V, 14.318MHz reference clock output.
"If FREQ_APIC = 0, APIC Clock = PCICLK
If FREQ_APIC = 1, APIC Clock = PCICLK/2 (default)"
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