ICS9179B-01 Datasheet, PDF (5/9 Pages) Integrated Circuit Systems – Low Skew Buffers

ICS9179 B -01
Functionality
OE#
SDRAM (0:3)
0
Hi-Z
1
1 X BUF_IN
SDRAM (4:7)
Hi-Z
1 X BUF_IN
SDRAM (8:11)
Hi-Z
1 X BUF_IN
SDRAM (12:15) SDRAM (16:17)
Hi-Z
Hi-Z
1 X BUF_IN
1 X BUF_IN
Byte 1: SDRAM Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
45
44
41
40
36
35
32
31
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
SDRAM15 (Act/Inact)
SDRAM14 (Act/Inact)
SDRAM13 (Act/Inact)
SDRAM12 (Act/Inact)
SDRAM11 (Act/Inact))
SDRAM10 (Act/Inact)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact))
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
Byte 2: PCICLK Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
28
21
-
-
-
-
-
-
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
SDRAM17 (Act/Inact)
SDRAM16 (Act/Inact)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes: 1 = Enabled; 0 = Disabled, outputs held low
ICS9179B-01 Power Management
The values below are estimates of target specifications.
Condition
No Clock Mode
(BUF_IN - VDD1 or GND)
I²C Circuitry Active
Active 66MHz
(BUF_IN = 66.66MHz)
Active 100MHz
(BUF_IN = 100.00MHz)
Max 3.3V supply consumption
Max discrete cap loads
VDD = 3.465V
All static inputs = VDD or GND
3mA
115mA
180mA
5