ICS9179B-01 Datasheet, PDF (1/9 Pages) Integrated Circuit Systems – Low Skew Buffers

Integrated
Circuit
Systems, Inc.
ICS9179 B -01
Low Skew Buffers
General Description
The ICS9179B-01 generates SDRAM clock buffers required
for high speed RISC or CISC microprocessor systems such as
Intel PentiumPro or Pentium II. An output enable is provided
for testability.
The device is a buffer with low output to output skew. This is
a Fanout buffer device, not using an internal PLL. This buffer
can also be a feedback to an external PLL stage for phase
synchronization to a master clock.
The individual clock outputs are addressable through I²C to
be enabled, or stopped in a low state for reduced EMI when
the lines are not needed.
Features
• High speed, low noise non-inverting (0:17) buffer for
SDRAM clock buffer applications.
• Supports up to four SDRAM DIMMS
• Synchronous clocks skew matched to 250 ps window on
SDRAM.
• I²C Serial Configuration interface to allow individual
clocks to be stopped.
• Multiple VDD, VSS pins for noise reduction
• Tri-state pin for testing
• Custom configurations available
• 3.0V – 3.7V supply range
• 48-pin SSOP package
Block Diagram
Pin Configuration
9179B-01 Rev C 05/18/98
48-Pin SSOP
PentiumPro is a trademark of Intel Corporation
I²C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.