ICS9176-01 Datasheet, PDF (5/8 Pages) Integrated Circuit Systems – Low Skew Output Buffer

ICS9176-01
AC Characteristics
PARAMETER
Input Clock Pulse Width ¹
Output Rise time, 0.8 to
2.0V ¹
Rise time, 20% to 80%
VDD ¹
Output Fall time, 2.0V to
0.8V ¹
Fall time, 80% to 20%
VDD ¹
Output Duty cycle ¹
Jitter, 1 sigma ¹
Jitter, absolute ¹
Input Frequency
Output Frequency
(Q outputs)
FBIN to IN skew ¹
Skew between any 2 out-
puts at same frequency ¹
Skew between any 1 out
put and Q/2 ¹
SYMBOL
TEST CONDITIONS
CLKW VDD=4.5V, fCLK=100 MHz
tr
15pF load
tr
15pF load
tf
15pF load
tf
dt
Tls
Tabs
fi
fo
tskew1
tskew2
15pF load
15pF load, Note 3
For outputs >100 MHz, use
Q/2 as feedback
Note 2, 4. Input rise time <
3ns
Note 2, 4.
tskew3
Note 2, 4
MIN
2.5
-
-
-
-
45
-
-250
20
20
-500
-250
-3
TYP
-
0.7
1.5
0.7
1.2
49/51
60
±100
-
-
250
50
±0.1
MAX
7.5
1
2
1
2
55
-
250
100
120
0
250
3
Notes:
1. Guaranteed by design and characterization. Not subject ot 100% test.
2. All skew specifications are measured with a 50W transmission line, load terminated with 50W to 1.4V.
3. Duty cycle measured at 1.4V.
4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs.
UNITS
ns
ns
ns
ns
ns
%
ps
ps
MHz
MHz
ps
ps
ns
5