ICS9176-01 Datasheet, PDF (3/8 Pages) Integrated Circuit Systems – Low Skew Output Buffer

Timing Diagrams
Timing in Divide by 1 Mode
ICS9176-01
Timing in Divide by 2 Mode
Timing in Eliminate by Test Mode
Note: In test mode, the VCOs are bypassed. The test clock input is simply buffered, then output. The part is transparent. Damage
to the device may occur if an output is shorted or forced to ground or VDD.
Timing in Power-down Mode
3