ICS9148-53 Datasheet, PDF (5/18 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Mother Boards

ICS9148 - 53
General I²C serial interface information
A. For the clock generator to be addressed by an I²C controller, the following address must be sent as a start sequence, with
an acknoledge bit between each byte.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
ACK
+ 8 bits dummy
command code
ACK
+ 8 bits dummy
Byte count
ACK
Then Byte 0, 1, 2, etc in
sequence until STOP.
D2(H)
B. The clock generator is a slave/receiver I²C component. It can read back the data stored in the latches for verification. (set
R/W# to 1 above) Read-Back will support Intel PIIX4 "Block-Read" protocol, with a "Byte count" following the
address with R/W#=1, then proceding to Byte 0, 1, 2, ...until STOP.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
ACK
Byte Count
Readback
Then Byte 0, 1, 2, etc. in
ACK _{sequence until STOP.}
D3(H)
C. The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
D. The input is operating at 3.3V logic levels.
E. The data byte format is 8 bit bytes.
F.
To simplify the clock generator I²C interface, the protocol is set to use only "Block Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
G. The Fixed clocks 48MHz and 24MHz are not addressable in the registers for Stopping. These output are always running,
except in Tristate Mode.
H. At power-on, all registers are set to a default condition. Byte 0 defaults to a 0, Bytes 1 through 5 default to a 1
(Enabled output state).
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