ICS9148-12 Datasheet, PDF (5/18 Pages) Integrated Circuit Systems – Pentium/ProTM System Clock Chip

Technical Pin Function Descriptions
CPU3.3_2.5#
This Input pin controls the CPU and IOAPIC output buffer
strength for skew matching CPU and SDRAM outputs to
compensate for the external VDDL supply condition. It is
important to use this function when selecting power supply
requirements for VDDL1,2. A logic “0” (ground) will indicate
2.5V operation and a logic “1” will indicate 3.3V operation.
This pin has an internal pullup resistor to VDD.
PWR_DWN#
This is an asynchronous active Low Input pin used to Power
Down the device into a Low Power state by not removing the
power supply. The internal Clocks are disabled and the VCO
and Crystal are stopped. Powered Down will also place all
the Outputs in a low state at the end of their current cycle.
The latency of Power Down will not be greater than 3ms. The
I²C inputs will be Tri-Stated and the device will retain all
programming information. This input pin only valid when
MODE=0 (Power Management Mode)
CPU_STOP#
This is a synchronous active Low Input pin used to stop the
CPUCLK clocks in an active low state. All other Clocks
including SDRAM clocks will continue to run while this
function is enabled. The CPUCLK’s will have a turn ON
latency of at least 3 CPU clocks. This input pin only valid
when MODE=0 (Power Management Mode)
PCI_STOP#
This is a synchronous active Low Input pin used to stop the
PCICLK clocks in an active low state. It will not effect
PCICLK_F nor any other outputs. This input pin only valid
when MODE=0 (Power Management Mode)
I²C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device in the
I²C protocol. It will allow read-back of the registers. See
configuration map for register functions. The I²C
specification in Philips I²C Peripherals Data Handbook
(1996) should be followed.
ICS9148-12
5