ICS87972I Datasheet, PDF (5/14 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
R_PULLUP
C_PD
R_OUT
Parameter
Input Capacitance
Input Pullup Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
ICS87972I
LOW SKEW, 1-TO-12
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Test Conditions
V_DDA, V_DD, V_DDO = 3.465V
Minimum
Typical
51
Maximum
4
Units
pF
KΩ
25
pF
7
Ω
TABLE 3A. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs
FSEL_A1 FSEL_A0
0
0
0
1
1
0
1
1
Outputs
QA
÷4
÷6
÷8
÷12
Inputs
FSEL_B1 FSEL_B0
0
0
0
1
1
0
1
1
Outputs
QB
÷4
÷6
÷8
÷10
Inputs
FSEL_C1 FSEL_C0
0
0
0
1
1
0
1
1
Outputs
QC
÷2
÷4
÷6
÷8
TABLE 3B. FEEDBACK CONFIGURATION SELECT FUNCTION TABLE
FSEL_FB2
0
0
0
0
1
1
1
1
Inputs
FSEL_FB1
0
0
1
1
0
0
1
1
FSEL_FB0
0
1
0
1
0
1
0
1
Outputs
QFB
÷4
÷6
÷8
÷10
÷8
÷12
÷16
÷20
TABLE 3C. CONTROL INPUT SELECT FUNCTION TABLE
Control Pin
VCO_SEL
REF_SEL
CLK_SEL
PLL_SEL
nMR/OE
INV_CLK
Logic 0
VCO/2
CLK0 or CLK1
CLK0
BYPASS PLL
Master Reset/Output Hi Z
Non-Inverted QC2, QC3
Logic 1
VCO
XTAL
CLK1
Enable PLL
Enable Outputs
Inverted QC2, QC3
87972DYI
www.icst.com/products/hiperclocks.html
5
REV. A OCTOBER 18, 2002