ICS8701 Datasheet, PDF (5/15 Pages) Integrated Circuit Systems – LOW SKEW ÷1, ÷2 CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8701
LOW SKEW ÷1, ÷2
CLOCK GENERATOR
TABLE 5A. AC CHARACTERISTICS, V_DD = V_DDO = 3.3V±5%, TA =0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
Maximum Input Frequency
t_PD
Propagation Delay; NOTE 1
0MHZ £ f £ 200MHz
2.2
tsk(b) Bank Skew; NOTE 2, 7
Measured on rising edge atV_DDO/2
tsk(o) Output Skew; NOTE 3, 7
Measured on rising edge atV_DDO/2
tsk(w)
Multiple Frequency Skew;
NOTE 4, 7
Measured on rising edge atV_DDO/2
250
MHz
3.4
ns
200
ps
250
ps
300
ps
tsk(pp) Part-to-Part Skew; NOTE 5, 7 Measured on rising edge atV_DDO/2
600
ps
t_R
Output Rise Time; NOTE 6
30% to 70%
280
850
ps
t
Output Fall Time; NOTE 6
F
odc
Output Duty Cycle
30% to 70%
0MHZ £ f £ 200MHz
280
850
ps
tCYCLE/2
- 0.5
tCYCLE/2
tCYCLE/2
+ 0.5
ns
f = 200MHz
2
2.5
3
ns
t_EN
Output Enable Time;
NOTE 6
f = 10MHz
6
ns
t_DIS
Output Disable Time;
NOTE 6
f = 10MHz
6
ns
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the 50% point of the input to the output crossing point.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages
and equal load conditions.
NOTE 5: Defined as the skew at between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the cross points.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
8701CY
www.icst.com/products/hiperclocks.html
5
REV. B AUGUST 2, 2001