ICS8701 Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – LOW SKEW ÷1, ÷2 CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8701
LOW SKEW ÷1, ÷2
CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
2, 5,
11, 26,
32, 35,
41, 44
7, 9, 18,
21, 28, 30,
37, 39, 46,
48
16, 20
25, 27,
29,
31, 33
34, 36,
38,
40, 42
43, 45,
47,
1, 3
4, 6,
8,
10, 12
22
Name
V_DDO
GND
V_DD
QA0, QA1,
QA2,
QA3, QA4
QB0, QB1,
QB2,
QB3, QB4
QC0, QC1,
QC2,
QC3, QC4
QD0, QD1,
QD2,
QD3, QD4
CLK
13
DIV_SELD
14
DIV_SELC
23
DIV_SELB
24
17, 19
15
DIV_SELA
BANK_EN1,
BANK_EN0
nMR/OE
Type
Power
Description
Output supply pins. Connect to 3.3V or 2.5V.
Power
Power supply ground. Connect to ground.
Power
Output
Positive supply pins. Connect to 3.3V.
Bank A outputs. LVCMOS interface levels.
W7 typical output impedance.
Output
Bank B outputs. LVCMOS interface levels.
W7 typical output impedance.
Output
Bank C outputs. LVCMOS interface levels.
W7 typical output impedance.
Output
Input
Input
Input
Input
Input
Input
Input
Bank D outputs. LVCMOS interface levels
W7 typical output impedance.
Pulldown
Pullup
Pullup
Pullup
Pullup
LVCMOS / LVTTL clock input.
Controls frequency division for bank D outputs.
LVCMOS interface levels.
Controls frequency division for bank C outputs.
LVCMOS interface levels.
Controls frequency division for bank B outputs.
LVCMOS interface levels.
Controls frequency division for bank A outputs.
LVCMOS interface levels.
Pullup Enables and disables outputs by banks. LVCMOS interface levels.
Pullup
Master reset and output enable. Enables and disables all outputs.
LVCMOS interface levels.
8701CY
www.icst.com/products/hiperclocks.html
2
REV. B AUGUST 2, 2001