ICS8533-01 Datasheet, PDF (5/13 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, V_CC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum Typical Maximum
PCLK
I
Input High Current
IH
nPCLK
V_CC = V_IN = 3.465V
V_CC = V_IN = 3.465V
PCLK
I_IL
Input Low Current
nPCLK
V_CC = 3.465V, V_IN = 0V
V = 3.465V, V = 0V
CC
IN
-5
-150
V_PP
Peak-to-Peak Input Voltage
0.3
V_CMR
Common Mode Input Voltage; NOTE 1, 2
V_EE + 1.5
V_OH
Output High Voltage; NOTE 3
V_CC - 1.4
V_OL
Output Low Voltage; NOTE 3
V_CC - 2.0
V_SWING Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Common mode voltage is defined as V_IH.
NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is V_CC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to V_CC - 2V.
150
5
1
V_CC
V_CC - 1.0
V_CC - 1.7
0.85
Units
µA
µA
µA
µA
V
V
V
V
V
TABLE 5. AC CHARACTERISTICS, V_CC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Maximum Output Frequency
650
t_PD
Propagation Delay; NOTE 1
IJ 650MHz
1.0
1.4
tsk(o) Output Skew; NOTE 2, 5
30
tsk(pp) Part-to-Part Skew; NOTE 3, 5
150
tjit(cc) Cycle to Cycle Jitter; NOTE 4, 5
150
t_R
Output Rise Time
20% to 80% @ 50MHz
300
700
t_F
Output Fall Time
20% to 80% @ 50MHz
300
700
odc
Output Duty Cycle
47
53
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ps
ps
ps
ps
ps
%
8533AG-01
www.icst.com/products/hiperclocks.html
5
REV. B JULY 16, 2001